Accelerating Nano-scale Transistor Innovation

Gerhard Klimeck, Purdue University

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Jun Huang, James Fonseca, Gerhard Klimeck, Rajib Rahman, Seung Hyun Park, Ryan Mokos, Zhengping Jiang, Parijat Sengupta, Yaohua Tan, Ganesh Hegde, Jean Sellier, Tillmann Kubis, Mykhailo Povolotskyi, Mehdi Salmani Jelodar, Hesameddin Ilatikhameneh, Daniel Mejia, Bozidar Novakovic, Daniel Lemus, Evan Wilson, Archana Tankasala, Ahmed Reza, Pengyu Long, Junzhe Geng, Yu Wang, Yu He, Yuling Hsueh, Saima Sharmin, Rifat Ferdous, Daniel Valencia, Fan Chen, SungGeun Kim, James Charles, Harshad Sahasrabudhe, Santiago Perez-Rubiano, Tarek Ameen, Prasad Sarangapani, Yuanchen Chu, Jose Bermeo, Kangliang Wei, Samik Mukherjee, Kuang-Chung Wang, Robert Andrawis, Chin-Yi Chen, Xinchen Guo, Devin Verreck, Frederico Marcolino Quintao Severgnini

One area of nanoscale semiconductor device physics that requires attention is device design. The downscaling of electronic devices has reached the range where the number of atoms in critical dimensions is countable, geometries are formed in three dimensions, and new materials are being introduced. Under these conditions the overall geometry constitutes a new material that cannot be found as such in nature. The interactions of electrons, photons, and lattice vibrations are now governed by these new material properties and longer-range interaction mechanisms such as strain and gate fields. Yet software tools currently in use have been designed for macroscale device simulation and have had various corrections added over the years.

The researchers plan to optimize and benchmark a new, already-implemented numerical algorithm, Low Rank Approximation (LRA) approach to speed computations. After optimization, it will be applied to devices of hundreds of thousands of atoms, thereby allowing atomistic simulation using relevant physics models for nanoscale devices.  

The goal is to use NEMO5 to calculate charge transport in nanowires, ultra thin body devices, and FinFETs (nanodevices that are relevant for the International Technology Roadmap for Semiconductors) under realistic incoherent scattering. The focus will particularly lie on computationally intense systems such as nanowire FETs of diameters above 15nm and UTBs and FinFETs including realistic contacts (metals, heavily doped semiconductors, leads on a large scale).

Klimeck vignette, originally prepared for NSF

https://engineering.purdue.edu/gekcogrp/